Regarding PCIE clock of Jetson TX2 - Jetson TX2 - NVIDIA Developer Forums
Selecting the Optimum PCIe Clock Source
PCI-e Reference Clock Measurement with Multiplexers
PCIE RC Use external reference clock - Jetson AGX Xavier - NVIDIA Developer Forums
PCI Express 3.0 needs reliable timing design - EDN
CDCM9102 data sheet, product information and support | TI.com
PCI Express 3.0 needs reliable timing design - EDN Asia
PCIe® Timing | Microchip Technology
PCI Express – Signal Integrity and EMI
9DBL0951 - 9-Output 3.3V PCIe Fanout Clock Buffer | Renesas
Effective Timing Strategies for Increasing PCIe Data Rates - EDN
PCI Express Clock Generators, Buffers Prepare for Next Generation | Electronic Design
PCI Express (PCIe) Clock Buffers - Diodes Inc | Mouser
What is PCI Express Clock gating?and is it worth keeping enabled? I have heard from quite a few people that keeping a number of these options enabled has caused Whea errors on
ZL30281 | Microsemi
PCI Express 3.0 needs reliable timing design - EDN
18329 - Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?
PCIe® Clock Buffers and Generators - IDT | DigiKey
PCI Express (PCIe) Clock Generators by IDT | DigiKey
PCI Express® Clocks | Renesas
Timing is Everything: How to optimize clock distribution in PCIe applications - Analog - Technical articles - TI E2E support forums
Using clock generators/buffers to adapt your PCIe design to specific application needs - Embedded.com
PCIe Timing ICs for Wireless 5G CPE Reference Design
The latest PCI Express 6.0 interface allows for 64Gb/s of data transfer in a single channel.
